VHDL LCD display animation


This is a school project from 2015 where a colleague and I were to familiarize ourselves with programming an FPGA using VHDL. We had the choice of a few different simple projects like "press button 1, LED 1 lights up, button 2, LED 2 lights up, etc" or something like that as well as being allowed to simply come up with our own project, which we did. Instead of using the LEDs as a display device, we devised a project which required learning to use the much more complicated 16x2 characters display. Ours is an animated message display over multiple lines with the possibility of changing the message displayed using the buttons.

LCD animation
LCD animation of one of the messages in our project


We were provided a development board based on Xilinx's Virtex 5 LX50T FPGA called Digilent's Genesys as well as Xilinx's synthesizer software (a computer program that turns VHDL into FPGA configuration code), which the Genesys board is explicitly compatible with.

Digilent Genesys development board
Digilent's Genesys development board (courtesy of Digilent)


FPGA means Field-Programmable Gate Array which sounds more like a programming structure than something tangible… but that's kind of exactly what it is. An FPGA is a integrated circuit which contains a bunch (an "Array") of various useful circuits such as full adders, muxers, etc all connected together many-to-many. The intent is that the customer is able to use software to specify how the various sub-circuits are to be arranged to specify which connections to disable and which to keep enabled thus effectively building a complex circuit tailored exactly to their specifications

Xilinx Virtex 5 FPGA
Connection schematic of Xilinx's Virtex 5 FPGA (courtesy of Digilent)


VHDL is a Hardware Description Language (HDL) which means its primary purpose is to describe electronic circuits both behaviorally and structurally. Considering what integrated circuits are meant to do, it is perhaps not too surprising that HDLs ended up being effectively programming languages although the name doesn't suggest as much. One important peculiarity of VHDL (and probably all HDLs) is that there is no sequentiality: everything happens all at once, all of the time although it is possible to detect signal changes through signal attributes (such as the {signal}'event attribute) and execute some code only during that. Thus state machines are a very useful construct along with if rising_edge(clk) blocks (which is a syntactic sugar to detect events, here on a clock signal)



The source code can be found here